送交者: sssa 于 2005-6-02, 18:04:11:
回答: 有效候选人何积丰教授 由 email 于 2005-6-02, 17:57:59:
"Formal Reasoning with Verilog HDL" (with G. Pace), in the Proceeding of Formal Method in Hardware Design, Spain, (1998).
This must be a 2- or 3- class conference even in Europe.